d2_3ad2_250_heterodyne_module
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- back_panel_markup.png
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- 2022/09/26 23:46
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- ethernet.png
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- 2022/09/20 22:27
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- 2022/09/27 20:07
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- 2022/09/27 20:07
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- fceo_3_locked.png
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- 2022/09/27 20:07
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- fopt_1_no-lock.png
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- 2022/09/27 20:07
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- fopt_2_locked.png
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- 2022/09/27 20:07
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- 2023/08/08 23:18
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- 2023/06/09 00:30
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- 2022/09/20 22:27
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- 2022/09/20 22:27
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- red_pitaya_locked_comb_schematic.png
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- 2022/09/20 22:23
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- 2022/09/26 23:26
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- settings_marked.png
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- 2022/09/20 22:39
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- settings.png
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- 2022/09/27 20:07
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- slice-fpga-ii_front_panel.png
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- 2023/05/03 16:50
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- slice-fpga-ii-rear.png
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- 2023/05/03 17:52
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- start_window_marked.png
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- 2022/09/20 22:41
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- updated_centering_fceo.png
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- 2023/06/09 21:19
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- updated_centering_fopt.png
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- 2023/06/09 21:24
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- updated_locking_fceo.png
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- 2023/06/09 21:19
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- updated_locking_fopt.png
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- 2023/06/09 21:24
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- winpython_terminal.png
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- 2023/06/09 18:09
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![[root]](/manuals/doku.php?id=d2_3ad2_250_heterodyne_module&ns=&tab_files=files&do=media&tab_details=history&image=ffc%3Aopt_pt_1.png){kind=link}
